The present invention relates to solid-state imaging apparatus using a multiple channel output system.
The multiple channel output systems made so as to concurrently obtain a plurality of video signals in parallel from a single imaging device have conventionally been employed as a general technique for obtaining the video signals at high frame rates from the imaging device having several million pixels. The high frame rates, however, are not necessarily required for example in the case of such imaging apparatus as a digital camera where still pictures are taken. There are also methods where the number of channels to be read is varied for example according to image taking situation.
FIG. 1 is a circuit diagram showing a portion of construction of imaging device disclosed in Japanese Patent Application Laid-Open 2004-328671 as an example of construction where the number of channels to be read is varied for example corresponding to image taking situation in a multiple channel output system of MOS imaging device. The imaging device as shown in FIG. 1 includes: unit pixels P1a to P2b each having photodiode PD1 serving as a photoelectric conversion section, an amplification transistor M1 for amplifying detection signal of the photodiode, a reset transistor M2 for resetting detection signal of the photodiode PD1, a row select transistor M3 for selecting each row of a pixel section, and a pixel power supply VDD; a vertical scanning section for driving the unit pixels P1a to P2b; a vertical signal line 3-A for outputting signal output of the unit pixels P1a and P2a; a vertical signal line 3-B for outputting signal output of the unit pixels P1b and P2b; biasing transistors M5A and M5B for respectively flowing a constant current through the vertical signal lines 3-A and 3-B; a bias current adjusting voltage line VBIAS for determining current values of the biasing transistors M5A and M5B; noise suppressing sections 10A and 10B connected to both ends respectively of the vertical signal lines 3-A and 3-B, for suppressing noise components of the signals of the unit pixels P1a to P2b; a column select transistor M1 3A for reading signals from the noise suppressing section 10A out to horizontal signal lines 15-1 and 15-2; a column select transistor M1 3B for reading signals from the noise suppressing section 10B out to horizontal signal lines 15-3 and 15-4; a horizontal scanning section 20 disposed at both sides of a pixel section with placing the pixel section between, for driving the column select transistors M1 3A and M1 3B; and output amplifiers 16-1 to 16-4 connected to terminal ends of the horizontal signal lines 15-1 to 15-4. The signals from the output amplifiers 16-1 to 16-4 are then fetched from output channels OUT1 to OUT4 as multiple channel output.
Here, the noise suppressing section 10A connected to the horizontal signal lines 15-1 and 15-2 includes: a clamping capacitor C1 1A connected to the vertical signal line 3-A or 3-B; a hold capacitor C1 2A for retaining change in voltage of the vertical signal line 3-A or 3-B; a sample-hold transistor M1 1A for connecting between the clamping capacitor C1 1A and hold capacitor C1 2A; and a clamping transistor M1 2A for clamping the clamping capacitor C1 1A and hold capacitor C1 2A to a predetermined voltage. A sample-hold control pulse φ SH1 is supplied to gate of the sample-hold transistor M1 1A, and a clamp control pulse φ CL1 is supplied to gate of the clamping transistor M1 2A.
Further, the noise suppressing section 10B connected to the horizontal signal lines 15-3 and 15-4 includes: a clamping capacitor C1 1B connected to the vertical signal line 3-A or 3-B; a hold capacitor C1 2B for retaining change in voltage of the vertical signal line 3-A or 3-B; a sample-hold transistor M1 1B for connecting between the clamping capacitor C1 1B and hold capacitor C1 2B; and a clamping transistor M1 2B for clamping the clamping capacitor C1 1B and hold capacitor C1 2B to a predetermined voltage. A control pulse φ SH2 is supplied to the gate of the sample-hold transistor M1 1B, and a control pulse φ CL2 is supplied to the gate of the clamping transistor M1 2B.
FIG. 2A schematically shows a drive timing chart of 4-channel mode for reading the signals of all pixels from the output channels OUT1, OUT2, OUT3, and OUT4 in the above prior-art example shown in FIG. 1. When a row select pulse of the first row φ ROW1 is driven to H level, the row select transistor M3 of the unit pixels of the first row is turned ON so that signal voltages of the unit pixels P1a and P1b of the first row are outputted respectively to the vertical signal lines 3-A and 3-B. At this time, the clamp control pulse φ CL1 and sample-hold control pulse φ SH1 are driven to H level to turn ON the sample-hold transistor M1 1A and clamping transistor M1 2A of the noise suppressing section 10A. The clamping capacitor C1 1A and hold capacitor C1 2A are thereby fixed to reference potential VREF.
Next, by driving the clamp control pulse φ CL1 to L level to turn OFF the clamping transistor M1 2A of the noise suppressing section 10A, the connecting line between the clamping capacitor C1 1A and hold capacitor C1 2A is brought into a floating state. Subsequently, the reset transistor M2 of the unit pixels of the first row is turned ON by driving the reset control pulse φ RES1 of the first row to H level to reset detection signal of photodiode PD1. Next, the reset control pulse φ RES1 is returned to L level again to turn OFF the reset transistor M2. At this time, voltage change Δ Vsig1 between before and after resetting photodiode PD1 occurs on the vertical signal lines 3-A and 3-B and is accumulated at the hold capacitor C1 2A through the clamping capacitor C1 1A and sample-hold transistor M1 1A.
Subsequently, the sample-hold control pulse φ SH1 is driven to L level to turn OFF the sample-hold transistor M1 1A. The signal component indicated by the following formula (1) is thereby retained as signal component of photodiode PD1 of the unit pixel of the first row at the hold capacitor C1 2A of the noise suppressing section 10A.VREF+{C1 1A/(C1 1A+C1 2A)}×ΔVsig1 . . .   (1)
Next, when the row select pulse φ ROW2 of the second row is driven to H level, the row select transistor M3 of the unit pixels of the second row is turned ON so that signal voltages of the unit pixels P2a and P2b of the second row are outputted respectively to the vertical signal lines 3-A and 3-B. At this time, the clamp control pulse φ CL2 and sample-hold control pulse φ SH2 are driven to H level to turn ON the sample-hold transistor M1 1B and clamping transistor M1 2B of the noise suppressing section 10B. The clamping capacitor C1 1B and hold capacitor C1 2B are thereby fixed to reference potential VREF.
Next, by driving the clamp control pulse φ CL2 to L level to turn OFF the clamping transistor M1 2B of the noise suppressing section 10B, the connecting line between the clamping capacitor C1 1B and hold capacitor C1 2B is brought into floating state. Subsequently, the reset transistor M2 of the unit pixels of the second row is turned ON by driving the reset control pulse φ RES2 of the second row to H level to reset detection signal of photodiode PD1. Next, the reset control pulse φ RES2 is returned to L level again to turn OFF the reset transistor M2. At this time, voltage change Δ Vsig2 between before and after resetting photodiode PD1 occurs on the vertical signal lines 3-A and 3-B and is accumulated at the hold capacitor C1 2B through the clamping capacitor C1 1B and sample-hold transistor M1 1B.
Subsequently, the sample-hold control pulse φ SH2 is driven to L level to turn OFF the sample-hold transistor M1 1B. The signal component indicated by the following formula (2) is thereby retained as signal component of photodiode PD1 of the unit pixel of the second row at the hold capacitor C1 2B of the noise suppressing section 10B.VREF+{C1 1B/(C1 1B+C1 2B)}×ΔVsig2 . . .   (2)
Finally, the horizontal select pulse φ H1 outputted from the horizontal scanning section 20 is driven to H level to turn ON the column select transistor M1 3A. The signal component retained at the hold capacitor C1 2A of the noise suppressing section 10A is read out respectively to the horizontal signal lines 15-1 and 15-2 and goes through the output amplifiers 16-1 and 16-2 so that the pixel signals of the unit pixels of the first row are read out respectively from the output channels OUT1 and OUT2. Concurrently, the column select transistor M1 3B is turned ON, whereby signal component retained at the hold capacitor C1 2B of the noise suppressing section 10B is read out respectively to the horizontal signal lines 15-3 and 15-4 and goes through the output amplifiers 16-3 and 16-4 so that the pixel signals of the unit pixels of the second row are read out respectively from the output channels OUT3 and OUT4. Similar operation is performed for a number of times equal to one half of the total number of the pixel rows so as to read the signals of all pixels from the output channels OUT1, OUT2, OUT3, and OUT4.
With the reading as the above in 4-channel mode, the signals of all pixels can be read out at high rate by using the four output channels to concurrently read two rows of pixel signal at a time.
FIG. 2B schematically shows a drive timing chart of 2-channel mode for reading the signals of all pixels only from the output channels OUT1 and OUT2 in the prior-art example shown in FIG. 1. When the row select pulse φ ROW1 of the first row is driven to H level, the row select transistor M3 of the unit pixels of the first row is turned ON so that signal voltages of the unit pixels P1a and P1b are outputted respectively to the vertical signal lines 3-A and 3-B. At this time, the clamp control pulse φ CL1 and sample-hold pulse φ SH1 are driven to H level to turn ON the sample-hold transistor M1 1A and clamping transistor M1 2A of the noise suppressing section 10A. The clamping capacitor C1 1A and hold capacitor C1 2A are thereby fixed to reference potential VREF.
Next, the connecting line between the clamping capacitor C1 1A and hold capacitor C1 2A is brought into floating state by driving the clamp control pulse φ CL1 to L level to turn OFF the clamping transistor M1 2A of the noise suppressing section 10A. Subsequently, the reset control pulse φ RES1 of the first row is driven to H level to turn ON the reset transistor M2 of the unit pixels of the first row so that detection signal of photodiode PD1 is reset. Next, the reset control pulse φ RES1 is returned to L level again to turn OFF the reset transistor M2. At this time, voltage change Δ Vsig1 between before and after resetting photodiode PD1 occurs on the vertical signal lines 3-A and 3-B and is accumulated at the hold capacitor C1 2A through the clamping capacitor C1 1A and sample-hold transistor M1 1A.
Subsequently, the sample-hold control pulse φ SH1 is driven to L level to turn OFF the sample-hold transistor M1 1A. The signal component indicated by the following formula (3) is thereby retained as signal component of photodiode PD1 of the unit pixel of the first row at the hold capacitor C1 2A of the noise suppressing section 10A.VREF+{C1 1A/(C1 1A+C1 2A)}×ΔVsig1 . . .   (3)
Finally, the column select transistor M1 3A is turned ON by H level of the horizontal select pulse φ H1 outputted from the horizontal scanning section 20. The signal component retained at the hold capacitor C1 2A of the noise suppressing section 10A is read out respectively to the horizontal signal lines 15-1 and 15-2 and goes through the output amplifiers 16-1 and 16-2 so that the pixel signals of the unit pixels of the first row are read out from the output channels OUT1 and OUT2. Similar operation is performed for a number of times equal to the total number of pixel rows so as to read the signals of all pixels from the output channels OUT1 and OUT2.
In 2-channel mode where the reading is effected as the above, factors of causing variance in characteristic can be reduced by reducing the number of channels-in the outputting so as to improve image quality. Power consumption can also be reduced by stopping operation of unnecessary circuits. As has been shown above, it is possible according to the prior-art technique to switch between image taking at high frame rate and image taking of high image quality and low power consumption by switching the number of output channels.